Data bus swizzling in TSV-based three-dimensional integrated circuits
نویسندگان
چکیده
The purpose of this paper is to efficiently exploit swizzling in reducing coupling noise between the bit lines of a TSV-based data bus in three-dimensional integrated circuits. The core concept of swizzling is to distribute the noise of an aggressor to all victims, rather than concentrating on the nearest victim. Based on this principle, an optimal swizzling pattern, which achieves an equal distribution of the coupling impedance, is proposed. The efficiency of this optimal pattern is demonstrated through comparison to no swizzling and two other swizzling patterns while considering different TSV diameters, aspect ratios, pitches, and transition times of the aggressor signal. A circuit model of a TSV-based 3-D data bus is evaluated in HSPICE with each TSV modeled as an RLC impedance. A maximum reduction of 51% in peak coupling noise is achieved. & 2013 Elsevier Ltd. All rights reserved.
منابع مشابه
An investigation into Cluster-based topologies for 3D Networks-on- Chip
A candidate to acquire better performance and package density can be introduced as three-dimensional integrated circuits, which this is compared to traditional two-dimensional. More specifically, a significant performance is obtained for 3D architectures through integrating schemes of Networks-on-Chip and advantages of 3D ICs. Since through-silicon-via (TSV) enables efficient inter-layer commun...
متن کاملAccurate TSV Number Minimization in High-Level Synthesis
Recent progress in process technology makes it possible to vertically stack multiple integrated chips. In three dimensional integration circuits (3D ICs), through silicon vias (TSVs) are used to communicate signals between layers. However, TSVs act as obstacles during placement and routing and have a negative impact on chip yield. Therefore, TSV number minimization is an important topic in 3D I...
متن کاملAdaptive 3D-IC TSV Fault Tolerance Structure Generation
In three dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, the yield and reliability is one of the key obstacles to adopt the TSV based 3D-ICs technology in industry. Various fault-tolerance structures using spare TSVs to repair faulty functional TSVs have been proposed in literature for yield and reliability ...
متن کاملAnalytical Modeling and Analysis of Through Silicon Vias (TSVs) in High Speed Three-Dimensional System Integration
This paper gives a comprehensive study on the modeling and design challenges of Through Silicon Vias (TSVs) in high speed three-dimensional (3D) system integration. To investigate the propagation characteristics incurred by operations within the ultra-broad band frequency range, we propose an equivalent circuit model which accounts for rough sidewall effect and high frequency effect. A closed-f...
متن کاملScaling trends of power noise in 3-D ICs
Power supply noise in three-dimensional integrated circuits (3-D ICs) considering scaled CMOS and through silicon via (TSV) technologies is the focus of this paper. A TSV and inductance aware cell-based 3-D power network model is proposed and evaluated. Constant TSV aspect ratio and constant TSV area penalty scaling, as two scenarios of TSV technology scaling, are discussed. A comparison of pow...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- Microelectronics Journal
دوره 44 شماره
صفحات -
تاریخ انتشار 2013